| 摘要 |
PURPOSE:To prevent generation of noise due to unstable output of a gate during its output inversion by giving a delay to either a clock signal or its complement signal more than the other. CONSTITUTION:The clock signal 13 outputted from a clock gate 4 is applied to the 1st NAND gate 1 through a delay means 69. Further, an input data 12 is inputted to the gate 1 and an output 15 of the gate 1 is inputted to the 3rd NAND gate 3. A latch output 17 being an output of the gate 3 is fed back to the input of the 2nd NAND circuit 2. The complement signal of the gate 4 is inputted to other input to the gate 2 and an output 16 of the gate 2 is inputted to the gate 3.
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