发明名称 DATA ACCESS SYSTEM OF MEMORY
摘要 PURPOSE:To read instantaneously as required either the page data of a jumping destination or the next page data out of a high-speed memory by reading out previously these two data at a high speed with a jump instruction. CONSTITUTION:A processor 1 reads successively the 3-page preceding data out of a bubble memory 5 and then sends both addresses on the 12th and n-th pages to a DMA circuit 3 in the form of pre-read addresses in case the 3-block preceding instruction is decided as a jump instruction. Then an access is given to the memory 5 to store data G12 and Gn on the 12th and n-th pages respectively to an RAM4. The processor 1 selects the data Gn with execution of the jump instruction and decides that the program of the branching destination needs 3-page preceding data Gn+1 and Gn+2. Thus the processor 1 sends these data to a DMA circuit 3 for a reading operation. It is discriminated that the data G12 of an area 4a of the RAM4 is not selected. Thus the area 4a is defined as the most preceding idle area to store the data Gn+1.
申请公布号 JPS59226947(A) 申请公布日期 1984.12.20
申请号 JP19830102231 申请日期 1983.06.08
申请人 FANUC KK 发明人 NAKAJIMA SEIICHIROU;TOYODA KENICHI;TORII NOBUTOSHI
分类号 G06F9/38;G06F12/00;G06F12/02;G06F12/08;(IPC1-7):G06F9/38;G06F13/00;G11C9/06 主分类号 G06F9/38
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