| 摘要 |
PURPOSE:To execute an access at a high speed without deteriorating a necessary function to KS by dividing the contents of a key storage part into the plural number by a logical field unit, controlling separately each part by providing an address register corresponding to the respective parts, and setting variably the timing of read and write of each part in accordance with a kind of an access operation to the key storage part. CONSTITUTION:A KS1 is divided into a KEY part 11 and an RC part 12, and they are accessed by a KSARK2 and a KSARR3 respectively. Also, a write data KSw data of a KS key instruction, etc. is inputted to the KEY part 11 and R, C of the RC part 12, and in case of an MS access, R, C of the RC part 12 are switched to the KSw data by multiplexers 13, 14, respectively, and MSr/w is inputted. In this case, in accordance with ''KS read'', ''KS write'' and ''MS access'' of an access operation to KS, the timing of read and write a logical field is set variably to execute series of pipeline control. |
