| 摘要 |
PURPOSE:To make a delaying buffer memory unnecessary in case of recording to a special VTR, in a device which is capable of processing a signal from a TV camera whose scaning speed is higher than a usual one, in the same way as a usual signal, by devising write and read-out in a speed converting circuit. CONSTITUTION:A clock CKN of 40.5MHz is supplied to a write address signal setting circuit 12, and an address signal whose speed is three times as high as a usual speed is formed. On the other hand, a clock CK0 of 13.5MHz is supplied to a read-out address setting circuit 13, and an address signal of a usual speed is formed. As for an access operation of these field memories, write and read-out are executed by time division, and apparently write and read-out can be executed at the same time. Also, at the same time as write of a high speed signal, its signal is immediately read out successively at a speed of 1/3 of a write time from each field memory. Accordingly, as for address signals ADR1- ADR3, the same address data is shifted successively by a 1/3 period portion each of a period FS and supplied.
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