发明名称 DUPLEX MEMORY CONTROL SYSTEM
摘要 PURPOSE:To execute the switching of a device by a hardware logic at the time of a fault by using a duplex primary memory on hardware as a single memory on software. CONSTITUTION:The output of an FF8 of a read-out memory selecting circuit 7 is ''0'' in an initial state, and a read-out memory selects a primary memory 1. In this state, when a read-out is executed from the primary memory 1, if abnormality is detected by a checking circuit 4, the FF8 is set, and as a result, as for the read-out memory, a primary memory 2 is selected. Also, when the abnormality is detected by the checking circuit 4 in a state that the primary memory 2 is selected, the FF8 is reset and the primary memory 1 is selected. The condition for executing the automatic selection of the primary memories 1, 2 is executed only when read-out system signals A, B are both ''0'', and when the system is designated, the automatic selection is not executed, the read-out is executed from the designated system, one system of the memory is separated, an access to the separated system at the time of one system operation due to a repair of a fault, etc. is inhibited, and copying after the repair can be executed.
申请公布号 JPS59227093(A) 申请公布日期 1984.12.20
申请号 JP19830099384 申请日期 1983.06.06
申请人 HITACHI SEISAKUSHO KK 发明人 TAGUCHI HARUKI
分类号 G06F12/16;G11C29/00 主分类号 G06F12/16
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