发明名称 INTEGRATED CIRCUIT FOR HIGH SPEED PARALLEL COMPARISON TYPE A/D CONVERSION
摘要 PURPOSE:To make an external additional circuit unnecessary, and to reduce cost by generating a basic clock signal synchronizing with the output data of an A/D converter, at the inside of an A/D converting integrated circuit. CONSTITUTION:DC voltage obtained by a ladder circuit 2 is applied as a reference voltage to each one terminal of a comparator 3, and in accordance with the magnitude of an analog input VIN, an output of the comparator 3 goes to ''1'', latched by a latch 4, and thereafter, decoded by an (n)-bit decoder. It is fetched as a digital output from a terminal 8 through a flip-flop 6 and an output driver 7. A fetching terminal 9 of an external synchronization SYNC is provided on this output driver 7, and a clock signal phi is led to the fetching terminal 9 through an invertor whose constitution is the same as that of said invertor for digital output, therefore, it is unnecessary to prepare an conventional external circuit and the cost is reduced.
申请公布号 JPS59226516(A) 申请公布日期 1984.12.19
申请号 JP19830102255 申请日期 1983.06.08
申请人 SUWA SEIKOSHA KK 发明人 ARASE KENJIROU
分类号 H03M1/36;(IPC1-7):H03K13/175 主分类号 H03M1/36
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