| 摘要 |
PURPOSE:To prevent occurrence of phase deviation by observing a dividing ratio of a counter means that divides a clock pulse and outputs a reference signal and resetting the counter means forcibly when the dividing ratio exceeds the preset maximum dividing ratio. CONSTITUTION:When the maximum dividing ratio nRX of a dividing ratio determining circuit 13 is n, and dividing ratio data nR is set to n-4 at timing T4, a counter output nC became already n-2, and therefore, a reset pulse SR is not outputted already. On the other hand, when a counter output nC becomes n+1 at timing T6, a reset pulse SR1 is outputted by a matrix circuit 21, and thereby a counter circuit 12 is reset. Accordingly, runaway of the counter circuit 12 caused when the reset pulse SR is not outputted from a coincidence circuit 14 can be suppressed, and temporary large deviation of the phase of reference signal SS from the phase of a synchronizing signal can be prevented.
|
