| 摘要 |
A read-only memory device comprises a plurality of groups of bit lines (BL0, BL1, . . . , BL63). One bit line within each group is selected by first column address decoders (4-1) and one group is selected by second column address decoders (8-0 DIFFERENCE 8-3). One load element (QL0, QL1, QL2, QL3) is provided in each second column address decoder to pull up the potentials of the bit lines.
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