发明名称 PLL SYSTEM DIGITAL FREQUENCY SYNTHESIZER
摘要 PURPOSE:To vary an output frequency in a minute step without decreasing a phase comparison frequency than a frequency of a voltage controlled oscillator by forming a reference phase comparison frequency with a frequency divider having a rational number and a fixed frequency divider and dividing the frequency of the VCO by a frequency divider having the same frequency dividing ratio of the fixed frequency divider so as to form a feedback phase comparison frequency. CONSTITUTION:A frequency dividing circuit 6 is constituted by the cascade connection of a bit rate multiplier and its frequency dividing ratio is L/K (where; K and L are integral numbers). An output frequency of the frequency dividing circuit 6 becomes FXK/L, it is further frequency-divided by M at the fixed frequency divider 7 and its output frequency F K/L M is inputted to a reference input terminal A of the phase comparator 2. On the other hand, a value f/M where the oscillating frequency (f) of the voltage controlled oscillator VCO4 is divided by a frequency divider 8 having a frequency dividing ratio of M is inputted to a feedback input terminal B of the comparator 2. The comparator 2 compares the phase of both of the said inputs, its compared output becomes a control voltage Vd via an LPF3 so as to control the oscillating frequency (f) of the VCO4. Thus, a frequency of K F/L is outputted from a terminal OUT by controlling the oscillating frequency of the VCO4 so that the phase difference to the two input terminals A, B to the phase comparator 2 is zeroed.
申请公布号 JPS59225619(A) 申请公布日期 1984.12.18
申请号 JP19830101407 申请日期 1983.06.06
申请人 NIPPON DENKI KK 发明人 KIHARA TADASHI
分类号 H03L7/18;H03L7/183;H03L7/197;H04L7/033 主分类号 H03L7/18
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