发明名称 TIME DIVISION MULTIPLEX COMMUNICATION SYSTEM
摘要 PURPOSE:To attain economically multiplex communication of storage type asynchronous time division multiplex (STMD) for data communication and digitized voice by adding a control function to a CPU for controlling the STDM for the purpose of establishment and maintenance of synchronism, and also utilizing the substantial function of the STDM. CONSTITUTION:A data passing through a transmission line 3 is divided or collected to the side of an STDM line IF1-2 and of a voice digitizing device 4 by a control switching section 1-3 and the communication between data communication circuits 6 and 6' is conducted at the same time. The operation of the control switching section 1-3 is as follows: A pattern from a synchronism identification pattern transmission circuit 32 is transmitted at a master station 1A to a transmission data line 7 via switching gates 24, 22. This signal is led to a synchronism identification pattern reception circuit 33 at a slave station 1B via a switching gate 26, a buffer 29 and a switching gate 30 from a reception data line 13, the circuit 33 detects the reception and reports it to the CPU. The CPU generates a command to a switching control circuit 31 to control a reception timing forming circuit 25 and the switching gate 26 and transfers the mode to a fixed slot synchronous time division multiplex (TDM) operation. A signal time- dividing the synchronism identification pattern is led to the circuit 33.
申请公布号 JPS59225638(A) 申请公布日期 1984.12.18
申请号 JP19830100211 申请日期 1983.06.07
申请人 KOKUSAI DENKI KK 发明人 KANAYAMA KENICHIROU
分类号 H04J3/00;H04J3/16;H04J3/24;H04M11/06;(IPC1-7):H04J3/00;H04L11/00;H04J6/02 主分类号 H04J3/00
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