发明名称 DIVISION ARITHMETIC CIRCUIT
摘要 PURPOSE:To simplify the constitution of hardware and also to improve an arithmetic speed by comparing a divided or a partial remainder and a divisor at a magnitude comparator circuit, and proceeding the processing from the result. CONSTITUTION:A divided register AR, divisor resiter BR and a quotient register CR storing respectively a divided, divisor and a quotient are constituted respectively as a two-way register. The magnitude comparator circuit COMP compares the content of the dividend register AR and the divisor register BR, the content of the divisor register BR is subtracted from the content of the dividend register AR from the result of comparison and the result of subtraction is returned to the dividend register AR. A timing control circuit TC controls that the content of the dividend register AR and the divisor register BR are compared sequentially by the magnitude comparator circuit COMP and transmits an output of the magnitude comparator circuit COMP to the quotient register CR and stores the result in it.
申请公布号 JPS59225448(A) 申请公布日期 1984.12.18
申请号 JP19830101269 申请日期 1983.06.06
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA 发明人 TAKENO MINORU;HASHIMOTO SHIYUUICHI;INDOU KIYOSHI;ISHIKAWA KOUICHIROU
分类号 G06F7/537;G06F7/52;G06F7/535 主分类号 G06F7/537
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