发明名称 SPEED DETECTING SYSTEM
摘要 PURPOSE:To enhance speed detecting speed over a total speed region, by calculating a speed by using the count value of a counter corresponding to a region to which an actual rotary speed belongs by counting a low speed clock pulse by a low speed counter while counting a high speed clock pulse by a high speed counter. CONSTITUTION:The pulse Pc generated from a rotary encoder 101 is subjected to wave form shaping by a wave form shaping circuit 102 to be converted to a pulse Pc' to be applied to a low speed cycle operating unit LSPU and a high speed cycle operating unit HSPU. On the other hand, the count value (n') of a counter 104' is transmitted to a second register 108'. A microprocessor 109 operates the cycle T of a pulse CT by using the numerical value (n') outputted from LSPU when s<=n and the numerical value (n) outputted from HSPU when s>n, a numerical value (s) is the boundary value of a high speed rotary region and a low speed rotary region. A rotary speed (v)(rpm) is outputted while operated by formula. In this case, P is the generation number of the pulse C generated per one rotation of the rotary encoder.
申请公布号 JPS59225356(A) 申请公布日期 1984.12.18
申请号 JP19830100444 申请日期 1983.06.06
申请人 FANUC KK 发明人 KURAKAKE MITSUO;KINOSHITA JIROU
分类号 G01R23/10;G01P3/489;(IPC1-7):G01P3/489 主分类号 G01R23/10
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