发明名称 PIN GRID ARRAY TYPE PACKAGE
摘要 PURPOSE:To reduce electrostatic destruction of a semiconductor element by a method wherein lead pins of different lengths of two kinds or more are provided, and input/output terminals apt to receive electrostatic destruction are connected to the lead pins of the shorter side thereof. CONSTITUTION:Long lead pins 33 and short lead pins 34 are provided to a package to load a semiconductor element, etc., and input/output lead pins to receive electrostatic destruction are provided by brazing on the back of a ceramic package base as to enable to be connected to the pins shorter by the degree of 0.5-1.0mm. as compared with the other pins. The construction of the main body of a package as well as the pins 33 of the longer side are constructed favorably as usual the same completely.
申请公布号 JPS59225551(A) 申请公布日期 1984.12.18
申请号 JP19830101143 申请日期 1983.06.06
申请人 MATSUSHITA DENSHI KOGYO KK 发明人 OKAMOTO TOMIO
分类号 H01L23/50;H01L23/498;H01L23/60;H05K1/02;H05K3/30;(IPC1-7):H01L23/48 主分类号 H01L23/50
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