| 摘要 |
PURPOSE:To form a control signal having high accuracy, stability and sureness by introducing the control signal to a DRAM by a clock signal using a delay device. CONSTITUTION:A write enable signal -WE as the control signal to the DRAM is outputted from an NAND gate 25, a row address strobe signal -RAS is outputted from an AND gate 21 and a column address strobe signal -CAS is outputted from an NAND GATE 22 respectively. A latch circuit forming the control signals like those is controlled by a clock signal CK or CKD1. Then the clock signal CK is obtained by a device clock signal and the clock signal CKD1 is formed by the clock signal CK and the delay device 30. Thus the control signal having high accuracy, safety and sureness is formed in this way.
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