发明名称 |
PICTURE INPUT DEVICE |
摘要 |
PURPOSE:To shorten a processing time for a system where a frame memory address is controlled by a register by updating an address without executing an address control instruction. CONSTITUTION:An up/down counter is used to an address register 18 connected to an interface bus 2 of a processor 1. Plural occupied addresses are set within a memory area of the processor 1. Then the update direction of the register 18 is decided by the position of an address where the frame memory data is read and written. Thus an address can be automatically updated in an optional direction. |
申请公布号 |
JPS59223880(A) |
申请公布日期 |
1984.12.15 |
申请号 |
JP19830097874 |
申请日期 |
1983.06.03 |
申请人 |
HITACHI SEISAKUSHO KK;HITACHI ENGINEERING KK |
发明人 |
ISHIKAWA KIYOSHI |
分类号 |
G09G5/00;G06F12/00;G06F12/02;G06F12/06;G06T1/60;G09G5/393;G09G5/395;(IPC1-7):G06F15/20;G09G1/00;G06F13/00 |
主分类号 |
G09G5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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