发明名称 |
ARITHMETIC AND LOGIC UNIT |
摘要 |
PURPOSE:To prevent the actuation of an arithmetic and logic unit as a whole even though one of plural operators has a fault by providing a fault detecting circuit and a queuing operator to the arithmetic and logic unit containing plural operators of the same type connected in series. CONSTITUTION:A fault detecting circuit 4 added newly detects the fault of an operator 1-j among those 1-1-1-N. Then a controller 5 replaces the faulty operator 1-j with a newly added queuing operator 1-N+1. Thus the actuation is not discontinued with subsequent operators. Switches 6 and 7 are cut off after the fault is repaired. Then the operators 1-j and 1-j+1 are connected by a switch 8-j to recover the actuation of a whole arithmetic device. |
申请公布号 |
JPS59223856(A) |
申请公布日期 |
1984.12.15 |
申请号 |
JP19830097840 |
申请日期 |
1983.06.03 |
申请人 |
HITACHI SEISAKUSHO KK |
发明人 |
FURUMURA FUMINOBU;HONMA KOUICHI;SETO YOUICHI;YAMAGATA NOBUTAKE;KUBO YUTAKA |
分类号 |
G06F7/00;G06F9/38;G06F11/20 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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