发明名称 CONTROL METHOD OF MULTI-PROCESSOR
摘要 PURPOSE:To prevent a simultaneous access to a shared memory by providing a lock signal generating flip-flop to a processor which has no TS instruction nor an instruction equivalent to said TS instruction. CONSTITUTION:The lock signal generating flip-flops F/F-A, and F/F-B are provided to processors PSC-A and PSC-B respectively for a multi-processor system containing plural processors connected to a shared memory CM. Then the read/ write is carried out for the lock byte of the memory CM, and the access given from one of two processors PSC-A and PSC-B is inhibited until a series of accesses given from the other processor are through. As a result, a lock function equivalent to a TS instruction can be obtained even in case both processors have no TS instruction nor an instruction equivalent to the TS instruction.
申请公布号 JPS59223873(A) 申请公布日期 1984.12.15
申请号 JP19830095795 申请日期 1983.06.01
申请人 TOSHIBA KK 发明人 KAKIHARA KENJI
分类号 G06F15/16;G06F9/52;G06F12/00;G06F13/16;G06F15/177;(IPC1-7):G06F15/16 主分类号 G06F15/16
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