发明名称 LAMINATED SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURE THERROF
摘要 PURPOSE:To enable to reduce the chip-to-chip wiring length and to contrive to enhance the mounting density by a method wherein the connection parts of active substrates are constituted of solder pads and interposing solder layers, which respectively oppose to each other, and a penetrating hole, whose inner surface has been coated with an insulating film and a conductive film, is provided on at least one side of the solder pads. CONSTITUTION:Groups of elements have been provided in the surfaces of chips 31 and 31' by selectively performing a doping and chip penetrating holes 32 and 32', etc., have been provided piercing through parts of the groups. Insulating films 33 and 33', such as an oxide film, etc., have been provided at the surfaces of the penetrating holes 32 and 32', and moreover, conductive coatings 34 and 34', which are provided at the upper parts thereof, and the substrates have been electrically separated. Solder bumps 35 and 35', which are used for connection with other chips, have been formed at the upper parts of wiring layers and the bump 35' of the lower chip has been provided opposite right to the bonding pad 34 having been extendedly provided from the opening part of the upper chip.
申请公布号 JPS59222954(A) 申请公布日期 1984.12.14
申请号 JP19830095729 申请日期 1983.06.01
申请人 HITACHI SEISAKUSHO KK 发明人 KETSUSAKO MITSUNORI
分类号 H01L23/52;H01L21/3205;H01L21/60;H01L23/48;H01L23/485;H01L25/065;H01L25/07;H01L25/18 主分类号 H01L23/52
代理机构 代理人
主权项
地址