发明名称 RESPONDING SYSTEM OF FACSIMILE
摘要 PURPOSE:To increase the number of the multiprocessing circuit of a responding device of facsimile and eliminate the necessity of parts having high processing capacities to the internal bus and control section, by selecting the data signal speed in accordance with the processing load of the responding device. CONSTITUTION:Numbers of circuits (numbers of terminals) transmitting at speeds of 9600, 7200, 4800, and 2400 bps are represented as i, j, k, and l, respectively and the number of disengaged circuits is represented as (m). However, the sum of all the numbers i, j, k, l, and m is 8. In this case, the speed (x) for newly transmitting to an n-circuit is selected in accordance with the following formula: 9600i+7200j+4800k+2400l+xn+2400(m-n). However, the processing capacity of a responding device 2 is set to 48kbps in terms of the total throughput of the eight circuits corresponding to terminals. When a computer 1 transfers a communication sentence to the responding device 2, the responding device 2 selects a speed x=4800bps by using the above- mentioned formula, if all the circuits are disengaged. In case where the computer 1 instructs terminals 3-5 to output communication sentences after the transfer is completed, the responding device 2 confirms that all the circuits are disengaged and selects another speed, 9600bps, by using the above mentioned formula. Moreover, when the computer 1 instructs terminals 6-8 to output communication sentences while the communication sentences are transferred to the terminals 3-5, the responding device 2 confirms that three circuits are engaged for the transmission at the speed of 9600bps and the other five circuits are disengaged, and selects 4800bps in the same manner.
申请公布号 JPS59223069(A) 申请公布日期 1984.12.14
申请号 JP19830095782 申请日期 1983.06.01
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 OGAWA HIROSHI;KODERA HIROSHI;KOSUGI MAKOTO
分类号 H04N1/32;(IPC1-7):H04N1/32 主分类号 H04N1/32
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