发明名称 MULTILAYER INTERCONNECTION METHOD
摘要 PURPOSE:To contrive to upgrade the processing precision on a contact hole and the processing precision on metal patterns by a method wherein after rough patterns generated by treating a crystal substrate were flatened by using spacer patterns and insulating material for embedding, the metal wiring patterns are processed by performing a performation processing on the patterns. CONSTITUTION:A source drain 101 and gate metal patterns 102 are formed on a GaAs crystal substrate 1 and spacer patterns 10 consisting of an insulating material of a nearly same height as these metal patterns 102 are formed without overlapping with the metal patterns 102. A liquid state-insulating material 11 is applied to the crystal surfaces. The material 11 is brought into a solid state while filling gaps G and the surfaces are flatened. By performing a perforation processing on the formed interlayer insulating layers 10 and 11, a second layer- metal pattern 201 is formed. Space patterns 20 consisting of an insulating material of a nearly same thickness as this are formed by performing a processing, and insulating material 21 for flatening and embedding is formed for being used as second interlayer insulating layers 20 and 21. By performing a processing for a contact hole on the second interlayer insulating layers 20 and 21, a third layer- metal pattern 301 is formed.
申请公布号 JPS59222944(A) 申请公布日期 1984.12.14
申请号 JP19830095724 申请日期 1983.06.01
申请人 HITACHI SEISAKUSHO KK 发明人 MIYAZAKI MASARU;KOBASHI TAKAHIRO
分类号 H01L21/3205;H01L21/60;(IPC1-7):H01L21/88 主分类号 H01L21/3205
代理机构 代理人
主权项
地址