| 摘要 |
PURPOSE:To simplify the constitution of a delay circuit behind a signal generating circuit and set its delay time easily over a wide range by easily extracting a desired signal which is delayed by an optional time from a sampling signal. CONSTITUTION:The variable delay circuit 4 is provided to a signal generator, data for delaying the sampling signal by DELTAt is set and held in the register 12 of the circuit 4, and a pulse signal from a pulse generating circuit 10 and an external sampling signal fs are applied to the counter 11. The output of this counter 11 and the output of the register 12 are applied to a register 13, and a delayed sampling signal DELTAt is applied to the address register 8 of the signal generating circuit 4 when the delay time of the DELTAt becomes equal to the counted value. The adding circuit 6 of this generating circuit 4 sums up setting data on the number of steps inputted externally to a register 5 and the delay signal from a register 8. A comparing circuit 7 compares a fixed sampled value with the output of the circuit 6, and the output of the register 8 is applied to a memory 9 according to the comparison result to set the delay time over a wide variation range. |
