发明名称 METHOD FOR TESTING DELAY EQUALIZING CIRCUIT
摘要 PURPOSE:To exclude a measuring terminal for disconnecting both a series and a parallel resonance circuit from the equalizing circuit by tuning the series resonance circuit to a prescribed frequency and changing the LC of the parallel resonance circuit so as to match the impedance of the input/output of a delay circuit. CONSTITUTION:The series resonance circuit is tuned to a turning frequency f01 by short-circuiting terminals 1,2 at first and adjusting an inductance L2 or a capacitor C2. Then terminals 2,6 are terminated by the characteristic impedance R0 of this circuit, an impedance mismatching attenuation measuring device 12 and a standard resistor Rs(=R0) are connected, and the maximum value (best value) of an impedance mismatching attenuation =(Zin-R0)/(Zin+R0) viewed from the terminals 1,5 is obtained by using them and adjusting the capacitor C2 and the inductance L2 at the tuning frequency f01. Thus this circuit allows to have the characteristic of the full band-pass circuit and the adjusting test of the 2nd order bridged T type delay equalizing circuit is attained.
申请公布号 JPS59221111(A) 申请公布日期 1984.12.12
申请号 JP19830096222 申请日期 1983.05.31
申请人 FUJITSU KK 发明人 ISHIZAKA TAEKO;OKAMURA HAJIME;KITOU AKIHITO
分类号 H03H7/01 主分类号 H03H7/01
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