发明名称 |
Flip-flop having improved synchronous reset. |
摘要 |
<p>A flip-flop is provided having a data gate circuit means (1) for receiving input data and generating therefrom first and second complementary internal data signals representative of the input data. A master circuit means (2) is coupled to the data gate circuit means for receiving a clock pulse and for latching the internal data signals during a predetermined portion of the clock pulse. A slave circuit means (3) is coupled to the master circuit means for storing the internal data signals. A reset means (23) supplies a synchronous reset signal to the master circuit means for resetting the first and second complementary internal data signals on the occurrence of the next clock pulse.</p> |
申请公布号 |
EP0127858(A1) |
申请公布日期 |
1984.12.12 |
申请号 |
EP19840105995 |
申请日期 |
1984.05.25 |
申请人 |
MOTOROLA, INC. |
发明人 |
BIRCH, WILLIAM A.;WOODARD, LILLIE M. |
分类号 |
H03K3/037;H03K3/289;(IPC1-7):03K3/037;03K3/281 |
主分类号 |
H03K3/037 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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