Self-aligned metal field effect transistor integrated circuits using polycrystalline silicon gate electrodes

摘要

A self-aligned metal process and resulting structure is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. All gate electrodes are composed of polycrystalline silicon while the remaining contacts are composed of metal. The insulation between the metal contacts and the polycrystalline silicon is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal/polycrystalline silicon and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A first layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are in those areas designated to be the gate regions of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is formed hereat. A second polycrystalline silicon gate electrode is formed over the gate dielectric and between certain of said narrow dimensioned regions. The remaining first polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions. A blanket layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached. The plastic material is then removed leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less. The source and drain electrodes are thusly formed.