| 摘要 |
A combined read-only storage (ROS) and read/write random access memory (RAM) integrated circuit memory cell is disclosed. In a first cell embodiment, a ROS FET device and a RAM FET device are connected in common to a bit sensing line connected to a sense amplifier which senses if the ROS FET device has discharged the bit sensing line indicating that a gate is present on the ROS FET device. A write driver circuit is also connected to the bit sensing line, for providing current through the RAM FET device to the charge storage element for writing a one or a zero therein. In a second cell embodiment, a combined two-bit read-only storage and one-bit read/write random access memory integrated circuit cell is disclosed. The bit sensing line is shared by two ROS FET devices and one RAM FET device. In a third cell embodiment of the invention, a single binary bit is stored for read-only storage and a single binary bit is stored for read/write random access memory storage. The charge storage element shares a common node with the ROS FET device and the RAM FET device and the sense amplifier is connected to the opposite side of the RAM FET device.
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