| 摘要 |
PURPOSE:To prevent the generation of an alpha-ray soft-error in a memory cell without increasing the generation of a latch-up in a circuit section of CMOS constitution by sufficiently deepening the junction depth of a well region in a CMOS circuit section while forming a memory cell circuit section in a shallow well region. CONSTITUTION:An n type well region 42 for a CMOS in deep junction depth d1 is formed to a peripheral circuit section 31 in a p type semiconductor substrate 41, and an n type well region 43 for preventing a soft error in shallow junction depth d0 is formed to a memory cell circuit section 31. Source-drain (p<+> diffusion layers 47) for a transistor are shaped in an element region isolated by a field oxide film 44 in the peripheral circuit section 31 through the implantation, etc. of an impurity. On the other hand, a p<-> diffusion layer 48 for a cell transistor, which functions as source-drain for the cell transistor and combines one electrode for a memory cell capacitor, is formed to the memory cell section 30, and a first polysilicon electrode 46 as the other electrode for the cell capacitor is shaped on the p<-> diffusion layer 48 through a gate oxide film 45, etc. |
