| 摘要 |
PURPOSE:To insert a parity bit with simple constitution by changing over the direction of transfer and adding a prescribed code after the transmission of a series signal is finished from a shift register having the capability for switching right and left transfer by means of a mode designating signal. CONSTITUTION:A shift register SFR' is advanced by 1 bit each to the right in synchronizing with a clock signal clk when a mode designating signal C2 transmitted from a counter circuit CNT is set to logical 0, and advanced by each 1 bit to the left in synchronizing with the signal clk when the signal C2 is set to logical 1. A parallel code consisting of 5 bits A-E is set to the register SFR', the circuit CNT counts the signal clk so as to set the signal C2 to logical 0 during the 1st-5th periods, sets the signal C2 to logical 1, and the signal is fed to the register SFR'. When the SFR' is advanced to the right and completes the output of the bits A-E serially, the register is advanced to the left by one step, a parity check code P is set to the most right stage from a parity code generating circuit PG and a serial code S2' with parity is outputted. |
