| 摘要 |
PURPOSE:To reduce the number of addresses by obtaining AND between an output of an ROM and input information by means of n-set of AND gates. CONSTITUTION:A row address signal (k) and a column address signal (i) are inputted to a memory 12 and output information aki<(j)>. This information aki<(j)> is inputted to n-set of AND gates 13 where the AND with information Xik inputted from an input terminal 11 is obtained. Information aki<(j)>.Xik obtained at an output of the AND gates 13 is multiplied and added at a part comprising n-set of exclusive OR gates 14 and a D flip-flop 15 and its result is fetched to the D flip- flop 15 in the timing of a clock signal T1'. When mn-set of information V11- Xmn are inputted, one code is produced at first and fetched and outputted by a clock signal T2' generated immediately after the Xmn is inputted. |
