发明名称 VIDEO SIGNAL BINARY-CODING CIRCUIT
摘要 PURPOSE:To prevent mis-reading by adding an analog delay circuit, an AND circuit and an OR circuit in addition to a peak hold circuit. CONSTITUTION:A sample-and-hold circuit 1 samples separately only a video signal from noise in an input signal IN and samples and holds it by a prescribed clock. A delay circuit 2 gives a prescribed time of delay to an analog signal A of the circuit 1 and outputs an analog signal B. An AND circuit 4 ANDs analogically the signals A, B. A peak hold circuit 3 follows a samll level of fluctuation of the peak value of the signal A and holds the peak value at large level fluctuation. An OR circuit 7 ORs analogically an output C of the circuit 3 and the signal A. A comparator 8 takes a value dividing an output E of the circuit 7 by a prescribed ratio as a reference compares an output F of the circuit 4 to binary-code. The ruggedness of the input signal is smoothed in the output F to include much black level component and to reduce noise due to dirt or the like.
申请公布号 JPS59218078(A) 申请公布日期 1984.12.08
申请号 JP19830092840 申请日期 1983.05.26
申请人 NIPPON DENKI KK 发明人 FUKASE TAKAYUKI
分类号 H04N5/14;H03K5/08;H04N1/403;(IPC1-7):H04N1/40 主分类号 H04N5/14
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