| 摘要 |
PURPOSE:To secure a timing of an interruption controller by providing an interruption request signal latching means which latches an interruption request signal from a sub-processor, inputs it to the interruption controller, and releases the input by a latch releasing signal. CONSTITUTION:A data exchange of a sub-processor SPn and a main processor MP is executed by using mail boxes MBXi-MBXm placed in a memory SMn as a unit. Sub-processor boards SBO-SBn-SBK are operated by a multi-task, and for instance, as for a line of an interruption request signal from the sub-processor board SBn, its output is inputted to an interruption request terminal of an interruption controller IRC through a latching circuit Ln corresponding to an interruption request signal in a main processor board MB. An interruption recognizing completion time in an interruption request time from the subprocessor SPn is secured by a fli-flop SPn in the latching circuit Ln.
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