| 摘要 |
PURPOSE:To execute write and read-out of N pieces of tracks by one memory at every read-out data transmission timing by taking a synchronization of a write address designation by a clock for executing a read-address designation. CONSTITUTION:A data reproduced by a magnetic head, etc. is inputted to a circuit block 50 provided on every track. A reference clock of 2ANfc (A is a rational number of >=1, and N is the number of tracks), whose time base variation is extremely small is inputted to a 1/2 frequency dividing circuit 80, and a write/ read-out time is set, and inputted to a read-out timing clock generator 82 and a write timing generator 84. FFs 66, 68 generate a write timing between the tracks by an output of the generator 84 and a transmission clock fc from a PLL 52. A read/write mode is designated by an output clock of the 1/2 frequency dividing circuit 80, and one of a write address or a read-out address whose track is designated is inputted to an address terminal of a memory 102.
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