发明名称 LOGICAL CIRCUIT
摘要 PURPOSE:To perform a test of a logical circuit including a register file with high efficiency by reading the contents of the register file with use of a write address stored in a normal mode as a read address. CONSTITUTION:A shift mode pin 3 is set at ''1'' to obtain a shift mode, and the same shift-in value is written to all slave flip-flops 14-17. Then the pin 3 is set at ''0'' to obtain a normal mode. Thus the data given from a data pin 1 via a master flip-flop 13 is written to a slave flip-flop shown by a write address. Finally the pin 3 is set at ''1'' again to obtain a shift mode. Then a shift-out action is carried out from an output pin 10. The contents of slave flip-flops shown by the addresses stored in the flip-flops 31 and 32 are shifted out to the pin 10 via a selector 18.
申请公布号 JPS59218548(A) 申请公布日期 1984.12.08
申请号 JP19830093140 申请日期 1983.05.25
申请人 NIPPON DENKI KK 发明人 SHIBANO HIDEO
分类号 G06F7/00;G01R31/317 主分类号 G06F7/00
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