发明名称 SIGNAL PROCESSING CIRCUIT OF COMBINATIONAL LOGIC TYPE
摘要 PURPOSE:To miniaturize the circuit by executing the multiplication and filtering two-series signals in time division at one circuit. CONSTITUTION:A sampled value xsi(nT) of a signal xsi is fetched to a signal converting circuit SPR at the final time slot of one sample period and a sampled value x(nT) of an input signal series is fetched in the time slot of the next sample period. A function circuit FUN forms a numeric table operating xXxsi by a prescribed algorithm. Then, the value of this numeric table is applied to an accumulator ACC2 via a switching circuit SEL2 so as to execute the calculation of xXxsi. Further, an output value of the accumulator ACC2 is given to a storage section MEM2 via a switching circuit SEL1 so as to attain the 1st filtering by using the primary, secondary delayed values and a function theta representing the filter characteristic. Then, the operation of the secondary value X2 and the secondary value X3 is attained in the succeeding time slots and the operating value filtering the xXxsi is outputted at the start of the next sampling period.
申请公布号 JPS59218031(A) 申请公布日期 1984.12.08
申请号 JP19830091463 申请日期 1983.05.26
申请人 ANRITSU DENKI KK 发明人 FURUYA NOBUO
分类号 H03H17/02;(IPC1-7):H03H17/02 主分类号 H03H17/02
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