| 摘要 |
PURPOSE:To reduce the number of system component parts by discriminating a bus exclusive possession request signal of each 1-chip CPU from other I/O port by a priority discriminating circuit, and sending back a bus exclusive possession possible response signal to each 1-chip CPU. CONSTITUTION:When a 1-chip CPU4 is required to access to an RAM3, a bus exclusive possession request signal RQO is generated through an I/O port in accordance with a priority discriminating circuit 7. On the other hand, when a 1-chip CPU5 and 6 are not generating said request signals RQ1, RQ2, the priority discriminating circuit 7 sends back a bus exclusive possession possible response signal ACKO to the 1-chip CPU4. The 1-chip CPU4 receives this signal through the I/O port, and thereafter, executes access to the RAM3. In this regard, when a necessary processing is ended, the bus exclusive possession request signal RQO is dropped, and the exclusive possession of the bus is abandoned. In this way, plural 1-chip CPUs are made possible to hold an external memory in common. |
