发明名称 SIGNAL PROCESSING CIRCUIT OF COMBINATIONAL LOGIC TYPE
摘要 PURPOSE:To attain filtering at the same time when plural signals are operated by fetching a signal processed for the operation in one time slot of time division and preparing a numeric table required for the operation. CONSTITUTION:The product sum between an output of a filter and an external signal is attained by using one circuit by way of the external signal so as to be used as a variable of product sum in place of an input/output value of the filter and its delayed value in taking notice that a calculating formula of the digital filter is the product sum between a fixed constant and the variable.
申请公布号 JPS59218030(A) 申请公布日期 1984.12.08
申请号 JP19830091462 申请日期 1983.05.26
申请人 ANRITSU DENKI KK 发明人 FURUYA NOBUO
分类号 H03H17/02;H03H17/04;(IPC1-7):H03H17/02 主分类号 H03H17/02
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