发明名称 INFORMATION PROCESSOR
摘要 PURPOSE:To improve the information processing capacity by providing a time band when the using right of a data bus is disused for a communication controller which performs the asynchronous control for transfer of data between a CPU and a memory device via a communication circuit. CONSTITUTION:A CPU1, an RAM2 and a floppy disk FDP3 are connected to a common BUS, and a communication controller CIP4 performs the asynchronous control to transfer data among said parts. Both the FDP3 and the CIP4 are constituted with a small microprocessor type logic respectvely and transfer data between the RAM2 and the FDP3 via the BUS with no use of the CPU. The CIP4 inhibits temporarily the bus using right before the next data transfer is started when a piece of data is received from a host computer. Then the bus is used again after a prescribed period of time, and the data is transferred among the CPU1, the RAM2 and the FDP3 while the bus using right is disused. Thus the information processing capacity is improved.
申请公布号 JPS59218531(A) 申请公布日期 1984.12.08
申请号 JP19830092267 申请日期 1983.05.27
申请人 HITACHI SEISAKUSHO KK 发明人 YABE EIICHI;KOIZUMI HIROYUKI
分类号 G06F13/372;G06F3/00 主分类号 G06F13/372
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