| 摘要 |
PURPOSE:To know the address of a substituted regular row (or column) which contains a defective bit even after assembling by constituting a redundancy circuit and a reading circuit so that the reading of a memory is inhibited only when a spare row (or column) is selected while an external control signal is fixed at a level ''L'', and observing the output state of the memory through a bit map. CONSTITUTION:When the external control (RC) signal impressed to an external terminal 8 is fixed at the level ''L'', the RC signal of a NOR gate 10 goes up to a level ''H'', and an MOSFET24 is cut off to turn off a sense amplifier circuit 18; and a signal of I/0 balance is not transmitted to an unshown output buffer circuit and correct memory data is not read out. Therefore, when the address of the substituted regular row (or column) is known, the external terminal 8 is fixed at the level ''L'' and the memory is operated with full addresses only to observe the output data. |
