Space division within computer branch memories

摘要

Cache memory structures are arranged to further alleviate the continually increasing memory latency or delay problem caused by the ever increasing speed of computer processors. In these memory structures, a plurality of separate and independent memory branches are extended from a common bus that passes from a hierarchical level immediately above the processor. Each memory branch is initiated with a cache memory unit and ascends hierarchically to the main memory. Other intermediate cache memory units may be disposed in the branches between the initial cache memory unit and the main memory thereof. Memory space division may be applied to the intermediate cache memory units or the relative information storage capacities thereof may be sized to alleviate the memory latency or delay problem still further.