| 摘要 |
PURPOSE:To alter the configuration of an MM system and disconnect a cache memory partially without stopping a processor porividing a store-in cache memory common to respective memory access requesting devices, and performing store-through operation to the cache memory and swap-out operation to the MM while operating the processor. CONSTITUTION:When a setting command for a store-through mode is generated, the cache memory 4 is placed in the same mode. When write access is attained, the swap-out operation of the block is started after writing to the memory 4 is performed even in case of a cache hit and a mishit. When the store-through mode is released, said mode of the memory 4 is reset and normal store-in operation is entered. When all swap-out commands are accepted, a cache control part 11 starts a swap-out control part 15, which has a cache address counter and generates swap-out commands for all blocks from the address ''0'' of the memory 4; and the control part 11 performs the same control from the memory 4 to MM1 or MM2 when a modify bit is ''1'' and does not perform the control when ''0''. A control part 15 sets a flag on generating said command. |
