| 摘要 |
PURPOSE:To decrease the number of input/output holding circuits as well as the number of signals delivered among circuits, by converting a signal line into a bus and the holding circuit into a RAM and repeating the reading actions with the same RAM and also the writing actions via a switch gate circuit. CONSTITUTION:The >=2 pairs of data where the integer multiples of the number of minimum parallel bits are defined as a pair with parallel 2 bits defined as the minimum unit are written to a RAM circuit 2 as an input. The data to be converted within the circuit 2 is read out and the conversion of format is carried out for change of distribution for each OR and AND of bits or minimum unit of bits between input data or between the input data and the old input data through a logic gate circuit 1 and a holding circuit 4. Then data are written again to the circuit 2. This action is repeated by times equivalent to the number of pairs of the minimum parallel unit bits forming a pair of data. Thus the output data is held and >=1 pairs of different formats are delivered. |
