发明名称 INTERRUPTION PROCESSING SYSTEM
摘要 PURPOSE:To shorten a processing time, and to determine an event priority order by making an event processing unnecessary when only a supervisor call instruction interruption is generated, and holding an interruption factor when plural event factors are generated. CONSTITUTION:When only a supervisor call instruction SVC interruption exists, an SVC instruction is executed when an instruction is being executed, and an FF 13 is set by making the SVC ''1''. When the instruction is ended, an EI signal is outputted, an AND gate 33 becomes on, and an FF 23 is set, but since said signal is not inputted to an OR gate 50, it is considered that there is no event factor. Subsequently, if an interruption factor of a completion type is generated when the SVC instruction is being executed, an MCK signal becomes ''1'', an FF 11 is set, the EI signal becomes ''1'' at the time point when the SVC instruction is ended, an FF 21 is set, and an output of the OR gate 50 becomes ''1''. Accordingly, it is considered that there is an event factor, and whether an instruction factor whose priority order is higher than that of an SVC interruption factor exists or not is checked. As a result, the interruption factor of the highest priority order is processed.
申请公布号 JPS59216253(A) 申请公布日期 1984.12.06
申请号 JP19830090668 申请日期 1983.05.25
申请人 HITACHI SEISAKUSHO KK 发明人 TAKEUCHI HIDENORI
分类号 G06F9/48;(IPC1-7):G06F9/46 主分类号 G06F9/48
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