发明名称 INTEGRIERBARES BUSORIENTIERTES UEBERTRAGUNGSSYSTEM
摘要 A monolithically integratable transmission system for binary information has at least one address source which is connected to at least one address sink via an address bus. The address sink is respectively allocated to a register means connected to a data bus. A clock generator generates a first clock signal and a non-overlapping, phase-shifted second clock signal. The address bus and the data bus are precharged during the first clock signal and access of an addressed register means to the data bus occurs during the second clock signal. In the time span between the two clock signals, the address bus is charged with the address signals by discharging.
申请公布号 DE3319980(A1) 申请公布日期 1984.12.06
申请号 DE19833319980 申请日期 1983.06.01
申请人 SIEMENS AG 发明人 GEIGER,GERHARD,DIPL.-ING.;STRAFNER,MIACHAEL,DIPL.-ING.
分类号 H04L25/02;G06F13/40;G06F13/42;(IPC1-7):06F7/00;06F13/00;06F3/04;04L25/02;11C8/00;06F1/04 主分类号 H04L25/02
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