| 摘要 |
PURPOSE:To improve a maintenance property in case of generation of a parity error of a memory by executing separately a detection of an error in an interruption stack area, and a detection of an error generated in other area of the memory. CONSTITUTION:A data read out to a register 2 from stack areas N-P of a memory 1 is checked by a parity checking circuit 3. If a parity error exists, an error detecting signal is sent out to an AND circuit 5 and 6. At the same time, addresses N-P of the stack area send a data to a NOT circuit 4 and the AND circuit 5 from a terminal A. Accordingly, the AND circuit 5 becomes on, and sends out a parity error generating signal from a terminal B. Also, if a parity error is generated in other area than the stack area of the memory 1, since the address is other than N-P, the address is not sent out to the terminal A, and an output of the NOT circuit 4 becomes ''1''. Accordingly, the AND circuit 6 becomes on and sends out a parity error generating signal from a terminal C. |
