| 摘要 |
<p>Circuit for generating a timing signal in a Manchester decoder. The circuit comprises an oscillator (10), a counter (14) for dividing signals derived from the oscillator, and a comparator (18) for comparing the times of transitions in the output signal of the counter with transitions in input Manchester data. To form a digital phase locked loop, gates (12 and 16) are provided for selectively adding a pulse to and subtracting a pulse from the pulses applied to the divider (14) by the oscillator (10) in dependence upon the relative timing determined by the comparator (18), in such manner as to lock the phase of the output signal of the counter onto the phase of the Manchester data. A squelch circuit is also provided for inhibiting phase control by the comparator (18) in response to a drop in signal strength of the received signal containing the Manchester data. </p> |
