发明名称 RESET CIRCUIT
摘要 PURPOSE:To attain surely the reset of the circuit by inserting a P channel FET of diode connection between the gate electrde of an N channel FET and a power supply. CONSTITUTION:Diodes 9, 12 fix the potential of points M and R to zero V when a power supply voltage is zero V. Further, the capacitance of a capacitor 8 is made larger than that of a capacitor 7 in order to avoid the potential at the point M from following the power supply voltage when the power supply voltage rises. After the application of power, the potential reaches V1 being the sum of respective therehold values of FETs 11, 13 and the voltage at the point R starts to decrease. Further, a voltage VH3 reaches a threshold value V11 of an inverter 14, a voltage VR4 at an output point rises to the power supply voltage from zero V and the circuit is reset.
申请公布号 JPS59215120(A) 申请公布日期 1984.12.05
申请号 JP19830089688 申请日期 1983.05.20
申请人 FUJI DENKI SOUGOU KENKYUSHO:KK;FUJI DENKI SEIZO KK 发明人 AKANUMA SHINICHI
分类号 H03K19/003;H03K17/22;(IPC1-7):H03K19/003 主分类号 H03K19/003
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