发明名称 Two parallel engines for high speed transmit IPSEC processing
摘要 The invention relates to a network interface system (2) for interfacing a host system (6) with a network (8). The network interface system (2) includes a bus interface system (6), a media access control system (10), and a security system (14). The network interface (2) offloads IPsec processing from the host system (6). According to the invention, the security system (14) includes two processors (20, 21.) for encrypting the outgoing data. Outgoing data packets are sent alternately to one or the other processor (20, 21), whereby transmission processing can be accelerated relative to receive processing.
申请公布号 GB2427806(A) 申请公布日期 2007.01.03
申请号 GB20060015760 申请日期 2005.02.26
申请人 ADVANCED MICRO DEVICES, INC 发明人 MARUFA KANIZ;JEFFREY DWORK;ROBERT WILLIAMS;MOHAMMAD Y MANIAR;SOMNATH VISWANATH
分类号 H04L29/06;H04L12/22 主分类号 H04L29/06
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