| 摘要 |
A data word of less than or equal to 2N bits is counted for the number of binary "1's" contained therein in log22N=N cycles of 3 steps each in a microprocessor. As a first step the data in a first register is logically ANDed in an arithmetic logic unit (ALU) with a mask constant from a first read only memory (ROM), with a first logical product result placed in a second register. As a second step the data from the first register is logically ANDed in the ALU with the same mask constant complemented, and a second logical product result is placed in the first register. Meanwhile, the first logical product result in the second register is shifted in a shift matrix in accordance with a shift count constant obtained from a second ROM. As a third step the shifted first logical product result from the shift matrix is ADDed in the ALU with the second logical product result from the first register, and a sum result is placed in the first register as data. During the N iterative cycles the mask constants of 2N bits progress (alternate 1's and 0's), (alternate pairs of 1's and 0's), . . . , (half 1's and half 0's) while the shift constants progress 20, 21, 22, . . . , 2N-1. After N iterative cycles of 3 steps each, the number of binary 1's in the original data word of 2N bits is in the first register.
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