| 摘要 |
<p>PURPOSE:To clear a main memory for a short time by a direct memory access permitting instruction from a CPU to a DMAC (direct memory access control circuit) by setting up a transfer request input terminal of an idle channel of the DMAC to an active state. CONSTITUTION:An active ''1'' level is set up in the transfer request input terminal RQ2 of the idle channel (the 3rd channel) of the DMAC 2. The address of an area to be cleared of the main memory 6 and word length to be cleared are set up in a transferring register and transferring word length register for the 3rd channel under the control of a CPU 1. The CPU 1 applies a direct memory access permission to a control register in the DMAC 2. Consequently, a direct memory access requesting signal DRG is sent to the CPU 1, a bus is interrupted by a response signal DGRN and direct memory access transfer is executed by the number of transfer words from the leading address of the main memory 6.</p> |
