| 摘要 |
A synchronous signal generator includes a counter controller for producing a control signal from a reference signal inputted thereto, and a counter circuit responsive to the control signal for generating a given cyclic signal. The counter controller accumulates each frequency of appearances of phase positions within a given period of time. When any of accumulated frequencies of the phase positions reaches to a given value from which the largest number of appearance times of the phase position is obtained, the counter controller supplies the counter circuit with the control signal. The counter circuit is reset or preset by the control signal. Since the probability that a phase position of the control signal is exactly coincide in time with a true phase position of the reference signal is very strong, the counter circuit can continue to repeat its cyclic count operation in synchronism with the control signal and yet being independent of the jittered reference signal.
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