发明名称 SEMICONDUCTOR DEVICE
摘要 PURPOSE:To enable to increase the integration of the complementary type MOS LSI by a method wherein the gate electrode has the three layer structure of high melting point metal, metallic silicide, and polycrystalline Si, and the P-channel region and the N-channel region are put in ohmic connection without a contact bridge. CONSTITUTION:On an element isolation field SiO2 11, the wiring layers of the P<+> polycrystalline Si 15, P<+> metallic silicide 17, and high melting point metal 18 are formed in the P-channel region, and those of the N<+> polycrystalline 14, N<+> metallic silicide 16, and high melting point metal 18 in the N-channel region. The wiring layers have the P-N junction in the first layer at the boundary but has more ohmic characteristics than in the high melting point metal of the third layer. Thereby, the contact bridge is unnecessitated, an Al wiring layer 20 insulated by the second field SiO2 19 can pass immediately above the polycrystalline Si wiring at the boundary between the P-channel and the N-channel. Therefore, since the margin for mask alignment in the contact bridge is not necessary, and the patterning of the Al wiring is not restricted, the high integration of said LSI is enabled.
申请公布号 JPS59213156(A) 申请公布日期 1984.12.03
申请号 JP19830088145 申请日期 1983.05.19
申请人 SUWA SEIKOSHA KK 发明人 KATOU TATSUMASA
分类号 H01L21/8238;H01L21/28;H01L21/3205;H01L23/52;H01L27/08;H01L27/092;H01L29/78;(IPC1-7):H01L27/08 主分类号 H01L21/8238
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